1. Field of the Invention
This invention relates generally to radio frequency receivers, and more specifically to balancing amplitude and phase of an in-phase signal with amplitude and phase of a quadrature-phase signal in a quadrature receiver.
2. Related Art
In a low-IF receiver, the baseband I-channel and Q-channel may have unequal group delays, which is typically caused by small differences in path length and/or caused by one or more mismatches between I-channel and Q-channel analog filters and/or caused by one or more mismatches between I-channel and Q-channel mixers. Any difference in path length between the I-channel and the Q-channel produces a phase versus frequency response that is linear. Any mismatch between I-channel and Q-channel analog filters produces a phase versus frequency response that is non-linear, i.e., varies with frequency over a bandwidth of a received signal. Any mismatch between I-channel and Q-channel mixers produces a phase versus frequency response that is also non-linear. In a low-IF receiver, any imbalance between an in-phase (I) signal and a quadrature-phase (Q) signal should be minimized to provide good image rejection. I/Q group delay mismatch is usually minimized by careful design of I/Q paths. However, in some known low-IF receivers, as many as seven (7) radio frequency (RF) bands are routed to the baseband portion of the receiver, which makes it more difficult to control the I/Q group delay in such receivers.
Known low-IF receivers employ I/Q amplitude and phase correction that comprises a two-step process consisting of a calibration step followed by a correction step. One known low-IF receiver provides a phase imbalance correction that is linear, but, disadvantageously, the phase imbalance correction does not vary with frequency. Therefore, the existing phase imbalance correction is band-limited to a region near a single calibration frequency, thereby disadvantageously reducing image rejection for a wideband interferer.
FIG. 1 is a simplified functional block diagram of a prior art receiver 102 including a prior art I/Q equalization circuit 135. The receiver 102 includes analog circuits 104 and digital circuits 106. The analog circuits 104 include an antenna 108 for receiving a digitally-modulated, non-spread-spectrum signal, and a low noise amplifier (LNA) 110. The LNA 110 is coupled to mixers 114 and 115. A local oscillator (LO) 112 is coupled to mixer 114 to produce an in-phase channel, or I-channel, signal. The local oscillator (LO) 112 is also coupled to mixer 115, via a 90° phase shifter 113, to produce a quadrature-phase channel, or Q-channel, signal. The pair of mixers 114 and 115 produces a phase and amplitude imbalance that is constant over the signal bandwidth. The analog circuits 104 include I-channel and Q-channel lowpass analog filters 116 and 117, analog amplifiers 118 and 119, and analog-to-digital (A/D) converters 122 and 123. The analog filters 116 and 118 produce a phase and amplitude imbalance that varies over the signal bandwidth. The digital circuits 106 include a downsampling filter 130 and 131 that is coupled to an output of the A/D converter 122 and 123 via a 5-bit wide data path 125. A prior art I/Q equalization circuit 135 is coupled to an output of the Q-channel downsampling filter 131 via a 15-bit wide data path 133. The prior art I/Q equalization circuit 135 has a real output 138 and an imaginary output 139. The real output 138 from the prior art equalization circuit 135 is added to an output 132 from the I-channel downsampling filter 130 at adder 142. An output from the adder 142 is coupled to an I-channel selectivity filter 146. The imaginary output 139 from the prior art I/Q equalization circuit 135 is coupled to a Q-channel selectivity filter 147. The outputs from the selectivity filters 146 and 147 are coupled to a demodulator signal processor 150.
FIG. 2 is a simplified functional block diagram of one known prior art I/Q equalization circuit 135. The equalization circuit 135 corrects for the frequency-independent phase imbalance due to mixer imbalance, for the frequency-dependent phase imbalance due to path length differences and for the frequency-dependent phase imbalance due to analog filter mismatch. Most of the frequency-dependent phase imbalance is caused by the analog filters 116 and 117. The I/Q equalization circuit of FIG. 2 uses a complex finite impulse response (FIR) filter 202 on the Q-channel path. The FIR filter 202 includes a set of delay elements 204, a set of complex multipliers 208 and a set of complex adders 212. In the prior art, the detection of group delay is accomplished by measuring the phase imbalance versus frequency response at several test frequencies. The pairs of phase imbalance/test frequency data are inputted into a set of equations that produce complex coefficients for the FIR filter 202. With prior art receivers, including the prior art receiver 102, a set of linear equations is required to convert measured phase imbalance values into FIR coefficients. In general, for a set of N complex coefficients, N pairs of (fN, phase_imbalance(fN)) are measured, and a set of linear equations (i.e., N-equations, N-unknowns) is solved. Disadvantageously, the complex finite impulse response (FIR) filter 202 uses complex coefficients (C0, C1, C2, . . . , CN-1), and therefore requires two multiplications (one for the coefficient real part, and one for the coefficient imaginary part), and the complex additions require real and imaginary additions.
FIG. 3 is a simplified functional block diagram of another known prior art I/Q equalization circuit 135, in which a complex FIR filter 301 is separated into two parts: a real FIR filter 303 followed by a complex multiplier 305 that has a single complex coefficient C0. The real FIR filter 303 includes a set of delay elements 304, a set of real multipliers 308 and a set of real adders 312. A real-valued output 316 from the real FIR filter 303 is fed into the complex multiplier 305. This simplification can be made only when the frequency-dependent phase imbalance has odd symmetry about f=0 Hz, which is usually the case. In a low-IF architecture, the complex multiplier 305 is often combined with a down-mixing operation (not shown).
Referring now to FIGS. 2 and 3, the equalization circuit 135 includes delay elements 204 and 304, multipliers 208 and 308, adders 212 and 312, and memory (not shown), all of which disadvantageously operate on relatively wide 15-bit data.